In a digital transmission network, a pulse stuffing method is used for multiplexing asynchronous signals. In a pulse stuffing method, destuffing processing is needed in a receiving end. Because a signal for which destuffing processing has been performed has a large jitter, this jitter needs to be suppressed.
Conventionally, as a suppression means of a destuffing jitter, as disclosed in patent document 1, a method using a memory and a digital phase locked loop (DPLL) has been formulated. In this method, a jitter included in input clock and input data can be suppressed by writing the input data in a memory once, reading the data from the memory using an output clock with less jitter, and then outputting it. Frequency synchronization is maintained between the input clock and the output clock by a DPLL so that the data discontinuity by the overflow or underflow of the memory does not occur.
Generally in a PLL (Phase Locked Loop), in order to make a pull-in time short, the loop bandwidth needs to be expanded. On the one hand, in order to suppress a jitter component of an input signal, the loop bandwidth needs to be narrowed so that the output clock does not follow the jitter of then input clock. The loop bandwidth is determined by the bandwidth of a loop filter mainly.
Accordingly, in a conventional jitter suppression circuit, in order to achieve a high jitter suppression effect, the bandwidth of the loop filter needs to be narrowed, and as a result, there is a problem that a pull-in time becomes long.
Also in a PLL, as disclosed in patent document 2, for the purpose of shortening a pull-in time and of improving stability when synchronized, a means to detect whether a phase difference between an input signal and an output signal is no smaller than a predetermined value or not, and change a parameter of a loop filter according to the detection result is being proposed.
Because a PLL is generally used to make an output signal phase-locked to an input signal, a phase error between the input signal and the output signal is small when they are in a synchronous state. Accordingly, the means to perform parameter change according to whether a phase error is no smaller than a predetermined value is effective in shortening a pull-in time and improving stability at the time of synchronization.
Additionally, as a related art, patent documents 3-7 are cited, for example.    [Patent document 1] Japanese Patent Application Laid-Open No. 1992-246939    [Patent document 2] Japanese Patent Application Laid-Open No. 1997-200049    [Patent document 3] Japanese Patent Application Laid-Open No. 2000-031953    [Patent document 4] Japanese Patent Application Laid-Open No. 2003-023353    [Patent document 5] Japanese Patent Application Laid-Open No. 2007-036366    [Patent document 6] Japanese Patent Application Laid-Open No. 1993-327782    [Patent document 7] Japanese Patent Application Laid-Open No. 1994-053821